Define HDL Macro via quartus command line

Option1:

quartus_map my_design --verilog_macro="a=2"

An example in Makefile:

============================================================
A_ID = ....
MAP_ARGS = --verilog_macro="a=$(A_ID)"
$(QUARTUS_MAP_BIN) $(MAP_ARGS) $(PROJECT) -c $(REVISION)


Note:  If the macro has been already defined in HDL, the definition here in command line won't override it.
So, make sure remove the definition in HDL.

To make simulation happy,

`ifdef MODEL_TECH
`define a 2
`endif

Option2:

in TCL script

set_global_assignment -name VERILOG_MACRO "a=2"