FPGA reset

Reset bridge circuit asserts asynchronously and deasserts synchronously.

Signal Integrity

A white paper from Mentor. Click following link to read the paper. It's in my dropbox.


Signal Integrity from Mentor

Define HDL Macro via quartus command line

Option1:

quartus_map my_design --verilog_macro="a=2"

An example in Makefile:

============================================================
A_ID = ....
MAP_ARGS = --verilog_macro="a=$(A_ID)"
$(QUARTUS_MAP_BIN) $(MAP_ARGS) $(PROJECT) -c $(REVISION)


Note:  If the macro has been already defined in HDL, the definition here in command line won't override it.
So, make sure remove the definition in HDL.

To make simulation happy,

`ifdef MODEL_TECH
`define a 2
`endif

Option2:

in TCL script

set_global_assignment -name VERILOG_MACRO "a=2"

Altera Qsys

• Improve performance by adding pipeline and also adopting packet layer for MM interface 

 Q: what about the latency of MM command?

• a Qsys can be re-used as a sub-system
• The conduit interface can be either connected within a Qsys or export to top, which is very good.
• The .v doesn't include the source files anymore. will need to adjust script to get rtl file list. 
• More adapters available for MM and ST interface. especially Avalon-ST Multiplexier and De-Multiplexier .......

Notes:

• If a Avalon-MM interface waits for waitrequest to be high before starting write/read, it may deadlock.  watirequest condition should be removed. but, write/read should still wait for waitrequest being de-asserted before complete. 
• Qsys doesn't  generate cpu.v which includes rtl source files and path.

Altera PLL re-configure

See Altera app note: AN507 - implement PLL reconfiguration in Cyclone III device
http://www.altera.com/literature/an/AN507.pdf

Basically, if only the freqency needs to be changed, the ALTPLL_RECONFIG megafunction can be used and connected with ALTPLL core.

ALTPLL_RECONFIG can have a init file which can be used to re-configure ALTPLL in runtime.

In terms of changing shift phase, it's a bit more work to do, which involves directly control of phase shift interface of ALTPLL_RECONFIG..............

State-Based trigger in Altera SignalTap

http://www.altera.com/support/examples/on-chip-debugging/signal-tap/signaltap2-design-examples.html

Note:  In example, the counter c1 should be added first prior to be used in state flow.

Quartus Makefile flow

Click image to enlarge...

Xilinx TCL Flow Example

# try.tcl
# usage: xtclsh try.tcl
# xtclsh is Xilinx tcl shell
# reference: http://www.xilinx.com/itp/xilinx10/books/docs/dev/dev.pdf
# -- details on commandline and tcl command to create and setup project
# http://www.doulos.com/knowhow/tcltk/xilinx/
# -- An good example

# From an existing project, a tcl script can be generated in ISE/project/generate tcl
# It could be usefull as a reference to write my own tcl script, especially to setup process properties.

# Some include file will need to be copied to working directory if they are needed to parse the architecture
# The include file which is included by other include file may need to be copied to working directory??
# Within cygwin terminal, xtclsh works, but from tcsh or xterm, it frozen.

# the following is oen of my example tcl script
# It works with ISE 12.1

if { $argc != 1 } {
puts "The tcl script requires one arguement ."
puts "For example, xtclsh main.tcl my_prj"
puts "Please try again."
} else {
set PRJ_NAME [lindex $argv 0]
}

project close

## put out a 'heartbeat' - so we know something's happening.
puts "\n$PRJ_NAME: Rebuilding ($PRJ_NAME)...\n"


# Remove existed project files
set proj_exts [ list ise xise gise ]
foreach ext $proj_exts {
set proj_name "${PRJ_NAME}.$ext"
if { [ file exists $proj_name ] } {
file delete $proj_name
}
}

# Build a new project
project new ${PRJ_NAME}.xise

# Set project properties
project set family spartan6
project set device xc6slx45t
project set package fgg484
project set speed -3


project set "Verilog Include Directories" "...." -process "Synthesize - XST"

# Add source file
source rtl_files_list.tcl

# Add constraint files
xfile add "my_prj.ucf"

# project set "Manual Implementation Compile Order" true

# Set project properties
#project set Top $proj_name

# Set process option
# TBD

project set "Cores Search Directories" "...."


project set "Macro Search Path" "...."

# Run implementation
process run "Implement Design"
process run "Generate Programming File"

# close project
project close

A good blog site to look at.
If you are doing EE stuff.

http://www.eetimes.com/electronics-blogs

Endian

Depending on which computing system you use, you will have to consider the byte order in which multibyte numbers are stored, particularly when you are writing those numbers to a file. The two orders are called "Little Endian" and "Big Endian".

The Basics

"Little Endian" means that the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address. (The little end comes first.) For example, a 4 byte LongInt

    Byte3 Byte2 Byte1 Byte0

will be arranged in memory as follows:

    Base Address+0   Byte0
   Base Address+1   Byte1
   Base Address+2   Byte2
   Base Address+3   Byte3

Intel processors (those used in PC's) use "Little Endian" byte order.

"Big Endian" means that the high-order byte of the number is stored in memory at the lowest address, and the low-order byte at the highest address. (The big end comes first.) Our LongInt, would then be stored as:

    Base Address+0   Byte3
   Base Address+1   Byte2
   Base Address+2   Byte1
   Base Address+3   Byte0

Motorola processors (those used in Mac's) use "Big Endian" byte order.

Spansion S29GL512N simulation model issue

There is a bug in the simulation model V1.3 and eariler. Not try any version newer.

When doing section erase, the RY should be de-asserted right after erase command, but instead, it is de-asserted after 50us.

Note: 50us is the timeout time of erase command. After this time, the device starts real erasing process.

Impact: If the RTL checks if the device is buys or not based on RY, this would give RTL wrong status.

Fix: de-asserte RY right after erase command.

CVS tag - delete, rename, remove

Deleting, moving, and renaming tags

Normally one does not modify tags. They exist in order to record the history of the repository and so deleting them or changing their meaning would, generally, not be what you want.

However, there might be cases in which one uses a tag temporarily or accidentally puts one in the wrong place. Therefore, one might delete, move, or rename a tag. Warning: the commands in this section are dangerous; they permanently discard historical information and it can difficult or impossible to recover from errors. If you are a cvsnt administrator, you may consider restricting these commands with taginfo (the section called “User-defined logging”).

To delete a tag, specify the -d option to either cvs tag or cvs rtag. For example:

cvs rtag -d rel-0-4 tc

deletes the tag rel-0-4 from the module tc.

When we say move a tag, we mean to make the same name point to different revisions. For example, the stable tag may currently point to revision 1.4 of backend.c and perhaps we want to make it point to revision 1.6. To move a tag, specify the -F option to either cvs tag or cvs rtag. For example, the task just mentioned might be accomplished as:

cvs tag -r 1.6 -F stable backend.c

By default CVS doesn't allow moving and deleting branch tags, as this should not be done without understanding the issues that this raises. To override this, specify the -B option on the command line.

When we say rename a tag, we mean to make a different name point to the same revisions as the old tag. For example, one may have misspelled the tag name and want to correct it (hopefully before others are relying on the old spelling). To rename a tag, first create a new tag using the -r option to cvs rtag, and then delete the old name. This leaves the new tag on exactly the same files as the old tag. For example:

cvs rtag -r old-name-0-4 rel-0-4 tc
cvs rtag -d old-name-0-4 tc

Handle rectangle in Emacs

Rectangle commands operate on rectangular areas of the text: all the characters between a certain pair of columns, in a certain range of lines. Emacs has commands to kill rectangles, yank killed rectangles, clear them out, fill them with blanks or text, or delete them. Rectangle commands are useful with text in multicolumn formats, and for changing text into or out of such formats.

When you must specify a rectangle for a command to work on, you do it by putting the mark at one corner and point at the opposite corner. The rectangle thus specified is called the region-rectangle because you control it in much the same way as the region is controlled. But remember that a given combination of point and mark values can be interpreted either as a region or as a rectangle, depending on the command that uses them.

If point and the mark are in the same column, the rectangle they delimit is empty. If they are in the same line, the rectangle is one line high. This asymmetry between lines and columns comes about because point (and likewise the mark) is between two columns, but within a line.

C-x r k

Kill the text of the region-rectangle, saving its contents as the “last killed rectangle” (kill-rectangle).

C-x r d

Delete the text of the region-rectangle (delete-rectangle).

C-x r y

Yank the last killed rectangle with its upper left corner at point (yank-rectangle).

C-x r o

Insert blank space to fill the space of the region-rectangle (open-rectangle). This pushes the previous contents of the region-rectangle rightward.

C-x r c

Clear the region-rectangle by replacing all of its contents with spaces (clear-rectangle).

M-x delete-whitespace-rectangle

Delete whitespace in each of the lines on the specified rectangle, starting from the left edge column of the rectangle.

C-x r t string

Replace rectangle contents with string on each line (string-rectangle).

M-x string-insert-rectangle string

Insert string on each line of the rectangle.