Wildcard Assignments and Collections in Quartus Timequest

To simplify the task of applying constraints to many nodes in a design, the Quartus II
TimeQuest Timing Analyzer accepts the “*” and “?” wildcard characters. Use these
wildcard characters to reduce the number of individual constraints you must specify
in your design.
The “*” wildcard character matches any string. For example, given an assignment
made to a node specified as reg*, the Quartus II TimeQuest Timing Analyzer
searches for and applies the assignment to all design nodes that match the prefix reg
with none, one, or several characters following, such as reg1, reg[2], regbank, and
reg12bank.
The “?” wildcard character matches any single character. For example, given an
assignment made to a node specified as reg?, the Quartus II TimeQuest Timing
Analyzer searches and applies the assignment to all design nodes that match the
prefix reg and any single character following; for example, reg1, rega, and reg4.
Both the collection commands get_cells and get_pins have three options that
allow you to refine searches that include the wildcard character. To refine your search
results, select the default behavior, the -hierarchical option, or the
-compatibility option.
Example 7–58. Setting Operating Conditions with a Tcl Object
set_operating_conditions 4_slow_1100mv_85c
Chapter 7: The Quartus II TimeQuest Timing Analyzer 7–77
Timing Analysis Features
© March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 3: Verification
1 The pipe character is used to separate one hierarchy level from the next in the
Quartus II TimeQuest Timing Analyzer. For example, | represents a hierarchical pin name with the “|” separating the hierarchy from
the pin name.
When you use the collection commands get_cells and get_pins without an
option, the default search behavior is performed on a per-hierarchical level of the pin
name; that is, the search is performed level by level. A full hierarchical name may
contain multiple hierarchical levels where a “|” is used to separate the hierarchical
levels, and each wildcard character represents only one hierarchical level. For
example,”*” represents the first hierarchical level and “*|*” represents the first and
second hierarchical levels.
When you use the collection commands get_cells and get_pins with the
-hierarchical option, a recursive match is performed on the relative hierarchical
path name of the form |. The search is performed on the
node name; for example, the last hierarchy of the name and not the hierarchy path.
Unlike the default behavior, this option does not limit the search to each hierarchy
level represented by the pipe character.
1 The pipe character cannot be used in the search with the get_cells
-hierarchical option. However, the pipe character can be used with the
get_pins collection search.
When you use the collection commands get_cells and get_pins with the
-compatibility option, the search performed is similar to that of the Quartus II
Classic Timing Analyzer. This option searches the entire hierarchical path and pipe
characters are not treated as special characters.
Assuming the following cells exist in a design:
foo
foo|bar
and the following pin names:
foo|dataa
foo|datab
foo|bar|datac
foo|bar|datad
Table 7–53 shows the results of using these search strings.
Table 7–53. Sample Search Strings and Search Results (Part 1 of 2)
Search String Search Result
get_pins *|dataa foo|dataa
get_pins *|datac
get_pins *|*|datac foo|bar|datac
get_pins foo*|* foo|dataa, foo|datab
get_pins -hierarchical *|*|datac (1)
get_pins -hierarchical foo|* foo|dataa, foo|datab
get_pins -hierarchical *|datac foo|bar|datac
get_pins -hierarchical foo|*|datac (1)
7–78 Chapter 7: The Quartus II TimeQuest Timing Analyzer
Timing Analysis Features
Quartus II Handbook Version 9.0 Volume 3: Verification © March 2009 Altera Corporation
Resetting a Design
Use the reset_design command to remove all timing constraints and exceptions
from the design under analysis. The command removes all clocks, generated clocks,
derived clocks, input delays, output delays, clock latency, clock uncertainty, clock
groups, false paths, multicycle paths, min delays, and max delays.
This command provides a convenient way to return to the initial state of analysis
without the need to delete and re-create a new timing netlist.
Cross-Probing
The cross-probing feature allows you to locate paths and elements from the
TimeQuest Timing Analyzer to various tools available in the Quartus II software (and
vice versa).
From the TimeQuest GUI, you can right-click any path in the View pane and select
either Locate Path or Locate.
The source is the element in the From Node column and the destination is the element
in the To Node column.
The Locate Path option allows you to located the data arrival path, default, of the
currently selected row. To locate the data required time path select a row in the data
required path panel.
1 The Locate Required Path command is available only when there is a path to show;
unless the user reports the clock path as well, there is probably only a single node in
the required path. In this case, the command is not available.
The Locate option allows you to locate the highlighted element.
The Locate Path and Locate commands can cross-probe to either the Chip Planner,
Technology Map Viewer, or Resource Property Editor. Additionally, the Locate Path
option can cross-probe to Critical Path Settings.
From the Critical Path Settings dialog box in the Chip Planner, you can cross-probe to
the TimeQuest Timing Analyzer to report critical paths in the design.
locate
Use the locate command in the Console pane to cross-probe to the Chip Editor,
Critical Path Settings, Resource Property Editor, and the Technology Map Viewer.
get_pins -compatibility *|datac foo|bar|datac
get_pins -compatibility *|*|datac foo|bar|datac
Note to Table 7–53:
(1) Due to the additional *|*| in the search string, the search result is