FPGA reset

Reset bridge circuit asserts asynchronously and deasserts synchronously.

Signal Integrity

A white paper from Mentor. Click following link to read the paper. It's in my dropbox.


Signal Integrity from Mentor

Define HDL Macro via quartus command line

Option1:

quartus_map my_design --verilog_macro="a=2"

An example in Makefile:

============================================================
A_ID = ....
MAP_ARGS = --verilog_macro="a=$(A_ID)"
$(QUARTUS_MAP_BIN) $(MAP_ARGS) $(PROJECT) -c $(REVISION)


Note:  If the macro has been already defined in HDL, the definition here in command line won't override it.
So, make sure remove the definition in HDL.

To make simulation happy,

`ifdef MODEL_TECH
`define a 2
`endif

Option2:

in TCL script

set_global_assignment -name VERILOG_MACRO "a=2"

Altera Qsys

• Improve performance by adding pipeline and also adopting packet layer for MM interface 

 Q: what about the latency of MM command?

• a Qsys can be re-used as a sub-system
• The conduit interface can be either connected within a Qsys or export to top, which is very good.
• The .v doesn't include the source files anymore. will need to adjust script to get rtl file list. 
• More adapters available for MM and ST interface. especially Avalon-ST Multiplexier and De-Multiplexier .......

Notes:

• If a Avalon-MM interface waits for waitrequest to be high before starting write/read, it may deadlock.  watirequest condition should be removed. but, write/read should still wait for waitrequest being de-asserted before complete. 
• Qsys doesn't  generate cpu.v which includes rtl source files and path.

Altera PLL re-configure

See Altera app note: AN507 - implement PLL reconfiguration in Cyclone III device
http://www.altera.com/literature/an/AN507.pdf

Basically, if only the freqency needs to be changed, the ALTPLL_RECONFIG megafunction can be used and connected with ALTPLL core.

ALTPLL_RECONFIG can have a init file which can be used to re-configure ALTPLL in runtime.

In terms of changing shift phase, it's a bit more work to do, which involves directly control of phase shift interface of ALTPLL_RECONFIG..............

State-Based trigger in Altera SignalTap

http://www.altera.com/support/examples/on-chip-debugging/signal-tap/signaltap2-design-examples.html

Note:  In example, the counter c1 should be added first prior to be used in state flow.

Quartus Makefile flow

Click image to enlarge...