How to: CVS merge from trunk to branch

cvs up -d -j HEAD

How to: CVS import without any ignore files

cvs import -Ii

How to generate Modelsim libs of Xilinx

From GUI
1. choose project
2. In design Utilites , choose Compile HDL Simulation Libraries
3. Right click, goto Process Properties
4. Set Simulator path properly, Choose Language to ALL/Verilog/VHDL
5. Run the utility

Command Line:
$(COMPXLIB_BIN) -s mti_se -l verilog -p $(MODELTECH_PATH) -w -arch spartan6 -lib simprim -lib unisim -lib xilinxcorelib -dir $(XILINX_LIB_PATH)

MODELTECH_PATH is the path of modelsim program, for example:c:/Modeltech_6.6a/win32 for 6.6a SE.



XILINX_LIB_PATH is the path for output

Note: glbl.v from Xilinx is also needed.



*Newer version of Modelsim may not work with the libs created by older version of Modelsim.


Note: For Xilinx, Modelsim 6.4a or older version is not supported. Use 6.4b.